1. Field of the Invention
The present invention relates to a demodulator that demodulates a digital modulated signal, and more particularly to a digital quadrature detection circuit that effects conversion on mutually orthogonal baseband signals from an intermediate frequency signal.
2. Description of the Related Art
In recent years, digital communication systems have become common in mobile communication such as PHS (personal handy phone system), and, with this, there has been a demand for receivers of high performance but small size and of low power consumption. One well known system for digital communication suited for mobile communication is .pi./4 shift QPSK (quadrature phase shift keying). QPSK is a system whereby data from the transmission end are arranged in four phases i.e. 0.degree., 90.degree., 180.degree., 270.degree. (or 45.degree., 135.degree., 225.degree., 315.degree.), and rotated by 45.degree. in each case with every symbol. In order to effect correct demodulation of the signal of such a system, at the receiving end there are prepared two carrier waves differing in phase by 90.degree., and a quadrature receiver is employed to demodulate with these respectively. The outputs obtained by demodulation by these carrier waves are termed the in-phase component and quadrature component.
FIG. 9 is a functional block diagram of a prior art digital quadrature detection circuit disclosed by Y. Yamamoto et al "Experimental Study of .pi./4 Shift QPSK Burst Demodulator" at the 1992 Electronic Information Communication Association of Japan Autumn Congress B-245. This digital quadrature detection circuit employs a pulse counting system, and, in contrast to an analogue quadrature detection circuit, the detector is constituted without using analogue components such as mixer, low-pass filter or A/D converter.
In FIG. 9, a signal received by an antenna, not shown, is input to a bandpass filter (BPF) 51. BPF 51 extracts only signals in the desired band and outputs these to limiter 52. The signal, whose amplitude has been restricted by limiter 52, is subjected, in-phase comparators (EXOR) 53a, 53b, to phase-comparison with two reference signals, namely, an in-phase reference signal and a quadrature reference signal, generated by a .pi./2 (90.degree.) phase shifter 61 and a frequency divider 60 that divides the reference clock pulse by 1/N in frequency. The outputs are then detected by counting for a fixed period by means of a reference clock input which is of sufficiently high rate with respect to the IF signal, in counters 54a, 54b. Instantaneous phase converter 55 then converts the in-phase and quadrature phase detection signals to instantaneous phases and phase difference calculator 56 then performs phase comparison with the signal one symbol previous, to produce a phase difference signal. This phase difference signal is then output to a bit period detector 63 as a bit reference signal, and is sampled at the period of the regeneration symbol clock by sampling means 57. The data is then regenerated by data regeneration means 58 whilst being corrected by frequency offset correction means 59.
However, in order to achieve miniaturisation and reduction of power consumption of the digital demodulator, it is most effective to eliminate or reduce the number of analogue components and A/D (analogue to digital) converters that effect the conversion from analogue to digital. The circuit shown in FIG. 9, in which a hard-limited IF signal is input in single-bit quantized form can cope with such demands and has the excellent advantages that it does not require an A/D converter and the quadrature of the carrier signal is stable.
With the conventional digital quadrature detection circuit of FIG. 9, the detector is constituted without employing analogue components such as mixer, low-pass filter or A/D converter, the demodulator can be miniaturised and some degree of reduction of power consumption can be achieved. However, in order to avoid lowering the error rate characteristic of the demodulator, in this system, counters 54a, 54b have to be operated with a high-rate clock of about 100 times the symbol clock frequency. As a result, the power consumption of the digital quadrature detection circuit of FIG. 9 comes to represent the largest share of the power consumption of the demodulator as a whole. Thus demands for further reduction in power consumption of the demodulator cannot be met.